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Circuit linearity calibration can represent a set of high-dimensional search problems if the observability is limited. For example, linearity calibration of digital-to-time converters (DTC), an essential building block of modern digital phaselocked loops (DPLLs), is an example of a high-dimensional search problem as difficulty of measuring ps delays hinders prior methods that calibrate stage by stage. And, a calibrated DTC can become nonlinear again due to changes in temperature (T) and power supply voltage (V). Prior work reports a deep reinforcement learning framework that is capable of performing DTC linearity calibration with nonlinear calibration banks; however, this prior work does not address maintaining calibration in the face of temperature and supply voltage variations. In this paper, we present a meta-reinforcement learning (RL) method that can enable the RL agent to quickly adapt to a new environment when the temperature and/or voltage change. Inspired by the Style Generative Adversarial Networks (StyleGANs), we propose to treat temperature and voltage changes as the styles of the circuits. In contrast to traditional methods employing circuit sensors to detect changes in T and V, we utilize a machine learning (ML) sensor, to implicitly infer a wide range of environmental changes. The style information from the ML sensor is subsequently injected into a small portion of the policy network, modulating its weights. As a proof of concept, we first designed a 5-bit DTC at the normal voltage (1V) and normal temperature (27℃) corner (NVNT) as the environment. The RL agent begins its training in the NVNT environment. Following this initial phase, the agent is then tasked with adapting to environments with different temperature and supply voltages. Our results show that the proposed technique can reduce the Integral Non-Linearity (INL) to less than 0.5 LSB within 10, 000 search steps in a changed environment. Compared to starting learning from a random initialized policy and a trained policy, the proposed meta-RL approach takes 63% and 47% fewer steps to complete the linearity calibration, respectively. Our method is also applicable to the calibration of many other kinds of analog and RF circuits. 

This paper presents a two-layer RF/analog weighting MIMO transceiver that comprises fully-connected (FC) multi-stream beamforming tiles in the RF-domain first layer, followed by a fully connected analog- or digital-domain baseband layer. The architecture mitigates the complexity versus spectral-efficiency tradeoffs of existing hybrid MIMO architectures and enables MIMO stream/user scalability, superior energy-efficiency, and spatial-processing flexibility. Moreover, multi-layer architectures with FC tiles inherently enable the co-existence of MIMO with carrier-aggregation and full-duplex beamforming. A compact, reconfigurable bidirectional circuit architecture is introduced, including a new Cartesian-combining/splitting beamforming receiver/transmitter, dual-band bidirectional beamforming network, dual-band frequency translation chains, and baseband Cartesian beamforming with an improved programmable gain amplifier design. A 28/37 GHz band, two-layer, eight-element, four-stream (with two FC-tiles) hybrid MIMO transceiver prototype is designed in 65-nm CMOS to demonstrate the above features. The prototype achieves accurate beam/null-steering capability, excellent area/power efficiency, and state-of-the-art TX/RX mode performance in two simultaneous bands while demonstrating multi-antenna (up to eight) multi-stream (up to four) over-the-air spatial multiplexing operation using proposed energy-efficient two-layer hybrid beamforming scheme. 

Digital phase-locked loops (DPLL) are finding new applications in highly demanding contexts such as frequency synthesis for millimeter-wave (mm-wave) communications and clock generation for ultra-high-speed wireline transceivers. In a typical DPLL, however, a time-to-digital converter (TDC) with fine time resolution, high linearity and high dynamic range is required to meet stringent noise and spur performance requirements, which negatively impacts the power consumption in a DPLL. A bang-bang phase-detector (BBPD) outperforms a multi-bit TDC in terms of its’ jitter-power tradeoff, but its’ highly non-linear phase detection characteristic limits the locking speed of the loop. This research explores the design and of a 60 GHz digital sub-sampling phase-locked loop that uses a BBPD loop for frequency tracking and a coarse TDC loop for fast frequency acquisition. A prototype of the DPLL is designed in a 28-nm CMOS technology with supporting evidence through extensive simulations.